Elink tx round robin #80
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NOTE: This arbiter always grant access on one port, even when there are no requests. oh_fifo_cdc deasserts its access_out when wait_in is high. Signed-off-by: Ola Jeppsson <ola@adapteva.com>
All tests in elink/dv/tests produces the same output as before, except for 'test_regs.emf' where the original code shows a Write-After-Read condition with the access to ERX_CFG. Tested for several hours on one board with epiphany-examples running in parallel with e-read and e-write (to bogus MMR address), no issues. I'm not 100% happy with this one, as far as I can understand the 'oh_fifo_cdc' code there's a chicken-egg problem between 'wait_in'/'access_out' when using 'access_out' as an input to an arbiter request line. I think it would be better if the FIFO also exported 'valid' (~empty). Now the arbiter must guess (round-robin) which port might have data (see note in oh_arbiter_rr3.v). Signed-off-by: Ola Jeppsson <ola@adapteva.com>
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All tests in elink/dv/tests produces the same output as before, except
for 'test_regs.emf' where the original code shows a Write-After-Read
condition with the access to ERX_CFG.
Tested for several hours on one board with
epiphany-examples running in parallel with e-read and e-write (to bogus
MMR address), no issues.
I'm not 100% happy with this one, as far as I can understand the
'oh_fifo_cdc' code there's a chicken-egg problem between
'wait_in'/'access_out' when using 'access_out' as an input to an
arbiter request line. I think it would be better if the FIFO also
exported 'valid' (~empty). Now the arbiter must guess (round-robin)
which port might have data (see note in oh_arbiter_rr3.v).