Verb is a verification library for digital hardware.
Verb builds on top of cocotb to provide functional verification techniques for digital hardware. Most notably, Verb allows one to define functional coverage nets and apply adapative coverage-driven test generation (CDG) for fast functional coverage closure.
- Install the repository as a Python package using
pip(or your favorite Python package manager):
pip install git+https://github.com/chaseruskin/verb.git
The following objectives drive the design choices behind building this library:
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Ease of use: Verifying the next design should be intuitive and easy to set up
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General-purpose: Be generic and allow the user enough control to support a wide range of designs, from purely combinational logic to control-flow architectures
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Increased productivity: Using the library should result in shorter times spent in the verification phase due to reusing highly modular components with insightful results
Some notable features include:
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Ability to enable coverage-driven test generation to help minimize the number of tests required to achieve a target coverage
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Supported coverage nets:
CoverPoint,CoverRange,CoverGroup,CoverCross
- Adaptive Test Generation for Fast Functional Coverage Closure: Research paper on an adaptive test generation technique
- cocotb: Coroutine based cosimulation testbench environment for verifying VHDL and SystemVerilog RTL using Python
- UVM: Universal Verification Methodology