Add RISC-V architecture support #1
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Port Osiris to RISC-V (64-bit), tested on T-Head C910 processor. Key changes: - Add RISCV target architecture to CMakeLists.txt - Implement RISC-V prolog/epilog with proper calling convention - Add RISC-V timing using rdcycle and fence instructions - Implement Spectre-RSB pattern using JAL/RET for RSB manipulation - Add fence.i for instruction cache synchronization - Handle SIGBUS for RISC-V misaligned memory accesses - Add T-Head C910 cache flush instructions (dcache.*, icache.*) - Update filters to recognize RISC-V cache instructions - Rename x86Instruction to Instruction for architecture independence - Add instruction generator script parsing riscv-opcodes format Build with: cmake -DARCH=RISCV .. Requires: Capstone 5+ with RISC-V support
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Ports Osiris to RISC-V 64-bit. Tested on T-Head C910.
Build:
cmake -DARCH=RISCV ..Requires: Capstone 5+ with RISC-V support