Greyscale Processor – MIPS-Based Load/Store Architecture

📌 Overview

This project implements a custom MIPS-based processor in Verilog, designed specifically for grayscale image processing. The architecture supports only LOAD and STORE instructions to minimize hardware complexity and is ideal for embedded systems where pixel-level memory manipulation is key.

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🧠 1. What is MIPS?

MIPS (Microprocessor without Interlocked Pipeline Stages) is a classic RISC-based architecture that is:

• Simple and modular
• Widely used in academic and embedded environments
• Based on fixed 32-bit instruction size

Instruction Types:

• R-Type – Register operations (e.g., add, sub)
• I-Type – Immediate or memory instructions (e.g., lw, addi)
• J-Type – Jump instructions (e.g., j, jal)

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🧩 2. MIPS 5-Stage Pipeline

The classic MIPS processor is divided into 5 pipeline stages:

Instruction Fetch (IF)

• Fetch instruction from memory
• IR = Mem[PC], then PC = PC + 4

Instruction Decode (ID)

• Decode opcode, register fields
• Read registers
• Sign-extend immediate

Execute (EX)

• ALU performs operation or address calculation

Memory Access (MEM)

• Access memory (lw/sw)

Write Back (WB)

• Write result back to register

3. Our Custom Minimalist MIPS Processor

This design removes non-essential logic and focuses on just two instructions:

• LOAD (opcode = 1)
• STORE (opcode = 0)

Key Features:

• Reduced components and logic gates
• No need for ALU control or branch logic
• Minimal instruction format
• Fewer clock cycles per instruction

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🧱 4. Components Used

• Program Counter (PC)
• Instruction Memory
• General Purpose Registers
• Data Memory (RAM)
• ALU (supports only addition)
• Sign Extend Unit
• Multiplexers (x3)
• Control Unit (1-bit opcode)
• Sequence Controller

[31] => Opcode (1-bit) [30:26] => Source Register (rs) [25:24] => (Removed - not needed) [23:16] => Target Register (rt) [15:0] => 16-bit Immediate (offset) Example Hex Instruction: 80010041

Binary Representation: 10000000_00000001_00000000_01000001

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⏱️ 6. Instruction Execution Flow

LOAD Instruction Flow:

FETCH → DECODE → READ → WRITEBACK → FETCH

STORE Instruction Flow:

FETCH → DECODE → WRITE → FETCH

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⚙️ 7. Step-by-Step Operation

Instruction Fetch (IF)

• Program Counter sends address to Instruction Memory
• Instruction is fetched and loaded into Instruction Register
• PC is incremented by 4

Instruction Decode (ID)

• Decode rs, rt, and offset
• Fetch values from register file
• Sign-extend offset

Execute / Address Calculation

• ALU calculates:

  Effective Address = Reg[rs] + SignExtend(offset)

Memory Access – LOAD

• Memory is accessed using the calculated address
• Value is routed via multiplexer to register writeback

Memory Access – STORE

• Value from Reg[rt] is written to memory at calculated address

Write Back (for LOAD only)

• Data from memory is written to target register (rt)

🧮 8. Optimizations

• Only 1-bit opcode (LOAD = 1, STORE = 0)
• Bits [25:24] removed – not required for 64-pixel test
• Supports:
  • Up to 256 registers via 8-bit rt
  • 65,536 memory locations using 16-bit offset

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🎯 9. Target Application – Grayscale Processing

This processor design is intended for use with a grayscale image unit, where only memory read/write operations are needed to process pixel data. It is extended or integrated with an image-processing pipeline on an FPGA or ASIC.

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📝 10. Summary

This project demonstrates a stripped-down, efficient version of a MIPS processor tailored for a specific embedded task—image data handling through LOAD/STORE instructions. The custom design highlights how reducing instruction sets and pipeline stages can lead to a practical processor for grayscale computation, without unnecessary control logic or complex datapaths.