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JS embedded Verilog

Status: Open.

#37 In drom/logidrom;

· drom opened on Feb 8, 2025

SVG working with Dark / Light mode

Status: Open.

#36 In drom/logidrom;

· drom opened on May 24, 2021

[Question] Testing logidrom

bug

Status: Open.

#35 In drom/logidrom;

· pidgeon777 opened on Apr 14, 2021

render wires

Status: Open.

#34 In drom/logidrom;

· drom opened on Jun 6, 2020

Symbol construction

Status: Open.

#33 In drom/logidrom;

· drom opened on May 24, 2020

DataPath or Control logic?

enhancement

Status: Open.

#32 In drom/logidrom;

· drom opened on May 10, 2020

How to widen the render area in schematic?

Status: Open.

#15 In drom/logidrom;

· CacahueteNC opened on Apr 23, 2020

draw flip flops with the assign command

enhancement

Status: Open.

#16 In drom/logidrom;

· parafux opened on Feb 28, 2020

Long signal names cropped

bug

Status: Open.

#30 In drom/logidrom;

· kimmoli opened on May 22, 2019

schematic editor suggestion

enhancement

Status: Open.

#31 In drom/logidrom;

· nachiket opened on Feb 21, 2018

LUT truth table to schematic converter

enhancement

Status: Open.

#14 In drom/logidrom;

· drom opened on Nov 26, 2016

Benchmark circuits

Status: Open.

#13 In drom/logidrom;

· drom opened on Sep 12, 2016