phy/rmii.py: added LiteEthPHYRMIISpeedDetect Module to automatically detects the speed (10Mbps or 100Mbps)

[trabucayre]

Current RMII policy regarding speed is based on LiteEthPHYRMII CTOR parameter or a CSRStorage. 10Mbps or 100Mbps are selected at build time and may be modified manually at runtime.

But Its not always easy and requires intervention.

To have an automatic approach some solutions are possibles:

• using rx_clk (an output PHY's pin): 2.5MHz for 10Mbps or 25MHz for 100Mbps. By counting number of ref clk between two rising edge it's possible to deduce frequency/speed. This pin is not always available.
• reading PHY registers via MDIO: but the information is PHY specific and the register address depends on the PHY.

Another solution, according to RMII protocol is to count the number of clock cycle during /J/ /K/ sequence (between crs_high rising edge and start of preamble (rx_data[0] goes high))
Here to screenshot of the counter and the delay between these transitions.

10Mbps

100Mbps

Difference between counter's values is a good solution to detect speed.
Note: threshold is configurable at build time with speed_counter_threshold parameter (and fixed to 20 by default)