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GNR, EMR, SPR, SRF, PTL, ARL, LNL, MTL, ADL, GLP, GLM: Release event updates #356

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Merged
edwarddavidbaker merged 11 commits into from
Dec 18, 2025
Merged

GNR, EMR, SPR, SRF, PTL, ARL, LNL, MTL, ADL, GLP, GLM: Release event updates #356

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a96d6bf
ADL: Release v1.36 event files
edwarddavidbaker Dec 17, 2025
d40cfa3
ARL: Release v1.15 event files
edwarddavidbaker Dec 17, 2025
210676c
EMR: Release v1.21 event files
edwarddavidbaker Dec 17, 2025
faa0384
GLM: Release v13 event files
edwarddavidbaker Dec 17, 2025
9b561b0
GLP: Release v1.01 event files
edwarddavidbaker Dec 17, 2025
c9ebc3f
GNR: Release v1.17 event files
edwarddavidbaker Dec 17, 2025
6c9f684
LNL: Release v1.20 event files
edwarddavidbaker Dec 17, 2025
81c4ce2
MTL: Release v1.19 event files
edwarddavidbaker Dec 17, 2025
e49581a
PTL: Release v1.03 event files
edwarddavidbaker Dec 17, 2025
bda7f1e
SPR: Release v1.36 event files
edwarddavidbaker Dec 17, 2025
93b6ef0
SRF: Release v1.14 event files
edwarddavidbaker Dec 17, 2025
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56 changes: 53 additions & 3 deletions ADL/events/alderlake_goldencove_core.json
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Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
{
"Header": {
"Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.",
"Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.35",
"DatePublished": "10/17/2025",
"Version": "1.35",
"Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.36",
"DatePublished": "11/17/2025",
"Version": "1.36",
"Legend": ""
},
"Events": [
Expand Down Expand Up @@ -3132,6 +3132,56 @@
"PDISTCounter": "NA",
"Speculative": "1"
},
{
"EventCode": "0x83",
"UMask": "0x08",
"EventName": "ICACHE_TAG.STALLS_ISB",
"BriefDescription": "ICACHE_TAG.STALLS_ISB",
"PublicDescription": "ICACHE_TAG.STALLS_ISB",
"Counter": "0,1,2,3",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"Precise": "0",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"PDISTCounter": "NA",
"Speculative": "1"
},
{
"EventCode": "0x83",
"UMask": "0x10",
"EventName": "ICACHE_TAG.STALLS_INUSE",
"BriefDescription": "ICACHE_TAG.STALLS_INUSE",
"PublicDescription": "ICACHE_TAG.STALLS_INUSE",
"Counter": "0,1,2,3",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"Precise": "0",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"PDISTCounter": "NA",
"Speculative": "1"
},
{
"EventCode": "0x87",
"UMask": "0x01",
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204 changes: 177 additions & 27 deletions ADL/events/alderlake_gracemont_core.json
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6 changes: 3 additions & 3 deletions ADL/events/alderlake_uncore.json
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Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
{
"Header": {
"Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.",
"Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.35",
"DatePublished": "10/17/2025",
"Version": "1.35",
"Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.36",
"DatePublished": "11/17/2025",
"Version": "1.36",
"Legend": ""
},
"Events": [
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6 changes: 3 additions & 3 deletions ADL/events/alderlake_uncore_experimental.json
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Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
{
"Header": {
"Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.",
"Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.35",
"DatePublished": "10/17/2025",
"Version": "1.35",
"Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.36",
"DatePublished": "11/17/2025",
"Version": "1.36",
"Legend": ""
},
"Events": [
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197 changes: 166 additions & 31 deletions ARL/events/arrowlake_crestmont_core.json
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60 changes: 57 additions & 3 deletions ARL/events/arrowlake_lioncove_core.json
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Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
{
"Header": {
"Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.",
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.14",
"DatePublished": "10/17/2025",
"Version": "1.14",
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.15",
"DatePublished": "11/20/2025",
"Version": "1.15",
"Legend": ""
},
"Events": [
Expand Down Expand Up @@ -3193,6 +3193,60 @@
"PDISTCounter": "NA",
"Speculative": "1"
},
{
"EventCode": "0x83",
"UMask": "0x08",
"UMaskExt": "0x00",
"EventName": "ICACHE_TAG.STALLS_ISB",
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache ISB-full",
"PublicDescription": "Cycles where a code fetch is stalled due to L1 instruction cache ISB-full",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"PEBScounters": "0,1,2,3,4,5,6,7,8,9",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"Precise": "0",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Equal": "0",
"PDISTCounter": "NA",
"Speculative": "1"
},
{
"EventCode": "0x83",
"UMask": "0x10",
"UMaskExt": "0x00",
"EventName": "ICACHE_TAG.STALLS_INUSE",
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache In use-full",
"PublicDescription": "Cycles where a code fetch is stalled due to L1 instruction cache In use-full",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"PEBScounters": "0,1,2,3,4,5,6,7,8,9",
"SampleAfterValue": "200003",
"MSRIndex": "0x00",
"MSRValue": "0x00",
"Precise": "0",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "0",
"Deprecated": "0",
"Equal": "0",
"PDISTCounter": "NA",
"Speculative": "1"
},
{
"EventCode": "0x87",
"UMask": "0x01",
Expand Down
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