A chisel3 wrapper for pulp-platform/fpnew. Use the same method how ucb-bar/ariane-wrapper wraps Ariane.
This project uses verilator to preprocess fpnew sources to get rid of compiler derivatives to create a self contained verilog file.
You can either:
- Add this project to subdirectory and update your
build.sbt. - Run
sbt publishLocaland use"jia.je" %% "fpnew" % "1.0-SNAPSHOT"in libraryDependencies.
- When pipelineStages is configured other than zero and verilator is used for simulation,
-Wno-BLKANDNBLKmust be passed to verilator. Seesrc/test/scala/fpnew/FPNewTest.scalafor usage with chisel-iotesters.
See LICENSE. This project wraps code from pulp-platform/fpnew which is licensed under SolderPad Hardware License.