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26 changes: 26 additions & 0 deletions examples/string_test.vhd
Original file line number Diff line number Diff line change
@@ -0,0 +1,26 @@
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity string_test is
generic (
str_constant : string := "this is a string";
std_test : std_logic_vector(4 downto 0) := "11011";
str1_constant : string := "this is also a string"
);
port (
reset, sysclk, ival : in std_logic;
str_port : in string;
str1_port : in string := "test_string";
str1_port : in std_logic_vector(3 downto 0) := "0101"
);
end string_test;

architecture rtl of string_test is
signal foo : string := "test string";
signal foo : std_logic_vector(2 downto 0) := "011";
constant foo1 : string := "test string1";
constant foo : std_logic_vector(2 downto 0) := "000";
begin
foo <= foo1;
end rtl;
2 changes: 1 addition & 1 deletion src/def.h
Original file line number Diff line number Diff line change
Expand Up @@ -47,7 +47,7 @@ typedef struct slist {
} data;
} slist;

enum vrangeType {tSCALAR, tSUBSCRIPT, tVRANGE};
enum vrangeType {tSCALAR, tSUBSCRIPT, tVRANGE, tSTRING};
typedef struct vrange {
/* int hi, lo; */
enum vrangeType vtype;
Expand Down
1 change: 1 addition & 0 deletions src/vhd2vl.l
Original file line number Diff line number Diff line change
Expand Up @@ -84,6 +84,7 @@ void getbasedstring(unsigned skip);
"unsigned" |
"std_logic_vector" |
"std_ulogic_vector" { return BITVECT; }
"string" { return STRTYPE; }
"real" { return REAL; }
"downto" { return DOWNTO; }
"to" { return TO; }
Expand Down
29 changes: 23 additions & 6 deletions src/vhd2vl.y
Original file line number Diff line number Diff line change
Expand Up @@ -206,6 +206,17 @@ slist *addsl(slist *sl, slist *sl2){
return p;
}

slist *addexprsl(slist *sl, expdata *ed, vrange *vr){
if (vr->vtype == tSTRING) {
sl=addtxt(sl,"\"");
sl=addtxt(sl,ed->sl->data.txt);
sl=addtxt(sl,"\"");
} else {
sl=addsl(sl,ed->sl);
}
return sl;
}

slist *addvec(slist *sl, char *s){
sl=addval(sl,strlen(s));
sl=addtxt(sl,"'b");
Expand Down Expand Up @@ -701,7 +712,7 @@ slist *emit_io_list(slist *sl)
}

%token <txt> REM ENTITY IS PORT GENERIC IN OUT INOUT MAP
%token <txt> INTEGER BIT BITVECT DOWNTO TO TYPE END
%token <txt> INTEGER BIT BITVECT DOWNTO TO TYPE END STRTYPE
%token <txt> ARCHITECTURE COMPONENT OF ARRAY
%token <txt> SIGNAL BEGN NOT WHEN WITH EXIT
%token <txt> SELECT OTHERS PROCESS VARIABLE CONSTANT
Expand Down Expand Up @@ -907,7 +918,7 @@ genlist : s_list ':' type ':' '=' expr rem {
for(;;){
sl=addtxt(sl,p->name);
sl=addtxt(sl,"=");
sl=addsl(sl, $6->sl); /* expr */
sl=addexprsl(sl, $6, $3);
sl=addtxt(sl,";\n");
p=p->next;
if(p==NULL) break;
Expand All @@ -928,7 +939,7 @@ genlist : s_list ':' type ':' '=' expr rem {
for(;;){
sl=addtxt(sl,p->name);
sl=addtxt(sl,"=");
sl=addsl(sl, $6->sl); /* expr */
sl=addexprsl(sl, $6, $3);
sl=addtxt(sl,";\n");
p=p->next;
if(p==NULL) break;
Expand Down Expand Up @@ -1057,6 +1068,12 @@ type : BIT {
$$=new_vrange(tSCALAR);
}
| BITVECT '(' vec_range ')' {$$=$3;}
| STRTYPE {
$$=new_vrange(tSTRING);
$$->nhi=addtxt(NULL,"63*8");
$$->nlo=addtxt(NULL,"0");
fprintf(stderr,"WARNING (line %d): string type treated as 64 byte vector.\n", lineno);
}
| NAME {
sglist *sg;

Expand Down Expand Up @@ -1187,7 +1204,7 @@ a_decl : {$$=NULL;}
sl=addtxt(sl,sg->name);
sl=addpost(sl,$5);
sl=addtxt(sl," = ");
sl=addsl(sl,$8->sl);
sl=addexprsl(sl, $8, sg->range);
sl=addtxt(sl,";");
if(sg->next == NULL)
break;
Expand All @@ -1203,7 +1220,7 @@ a_decl : {$$=NULL;}
sl=addtxt($1,"parameter ");
sl=addtxt(sl,$3);
sl=addtxt(sl," = ");
sl=addsl(sl,$8->sl);
sl=addexprsl(sl, $8, $5);
sl=addtxt(sl,";");
$$=addrem(sl,$10);
}
Expand Down Expand Up @@ -1711,7 +1728,7 @@ p_decl : rem {$$=$1;}
break;
}
sl=addtxt(sl," = ");
sl=addsl(sl,$8->sl);
sl=addexprsl(sl, $8, $5);
sl=addtxt(sl,";\n");
$$=addsl(sl,$10);
}
Expand Down