Add support for length attribute

[DanTGL]

No description provided.

[ldoolitt]

Looks promising. Do you have a test case you could add?
If you feel lazy, just send me the .vhd file and I can do the rest.

[ApexGP]

While b4967b3 correctly parses the NAME'length attribute, the impl is currently limited to cases where the width is a known constant. The logic fails for dynamic or generic ranges (e.g., W-1 downto 0) because it only checks sizeval. If sizeval is -1, the translator emits -1 in the Verilog code, which is incorrect.

You may verify the issue by the test case provided below:

-- length_attr.vhd
library ieee;
use ieee.std_logic_1164.all;

entity length_attr is
  generic (
    W : integer := 8
  );
  port(
    a     : in  std_logic_vector(W-1 downto 0);
    len_a : out integer
  );
end entity length_attr;

architecture rtl of length_attr is
begin
  len_a <= a'length;
end architecture rtl;

And get something like

assign len_a = -1;

It should ideally fall back to the range expression itself when the numeric width isn't static.

assign len_a = W;

[ApexGP]

@DanTGL I've managed to create a simple patch based on b4967b3, please follow the steps below to test it.

git fetch upstream && \
git pull upstream master && \
git apply length_formal.patch

The patch now prefers using size_expr (even if vtype is not tVRANGE).

• First evaluate size_expr, if present, copy and use it;
• Then fall back to using sizeval;
• Revert to 1 only if neither is available.

Simultaneously use copysl() to avoid potential side effects of sharing the size_expr pointer.