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@pfusik pfusik commented Dec 15, 2025

enumerated and non-enumerated type in conditional expression [-Wextra]

    enumerated and non-enumerated type in conditional expression [-Wextra]
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llvmbot commented Dec 15, 2025

@llvm/pr-subscribers-backend-risc-v

Author: Piotr Fusik (pfusik)

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enumerated and non-enumerated type in conditional expression [-Wextra]

Full diff: https://github.com/llvm/llvm-project/pull/172315.diff

1 Files Affected:

  • (modified) llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp (+5-4)
diff --git a/llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
index f1827dcf174f3..5eef1a998719f 100644
--- a/llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
@@ -232,11 +232,12 @@ bool RISCVLoadStoreOpt::tryConvertToXqcilsmLdStPair(
 
   unsigned XqciOpc = (Opc == RISCV::LW) ? RISCV::QC_LWMI : RISCV::QC_SWMI;
 
-  auto StartRegState = (Opc == RISCV::LW) ? RegState::Define
-                                          : getKillRegState(FirstOp0.isKill());
-  auto NextRegState =
+  unsigned StartRegState = (Opc == RISCV::LW)
+                               ? static_cast<unsigned>(RegState::Define)
+                               : getKillRegState(FirstOp0.isKill());
+  unsigned NextRegState =
       (Opc == RISCV::LW)
-          ? RegState::ImplicitDefine
+          ? static_cast<unsigned>(RegState::ImplicitDefine)
           : (RegState::Implicit | getKillRegState(SecondOp0.isKill()));
 
   DebugLoc DL =

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LGTM

@pfusik pfusik merged commit aea5dad into llvm:main Dec 15, 2025
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@svs-quic
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Thanks for fixing this.

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4 participants