Port nrf7120 upstream sdk zephyr

MAINTAINERS.yml

@@ -2509,6 +2509,7 @@ Documentation Infrastructure:
     - dts/bindings/wifi/nordic,nrf7000-spi.yaml
     - dts/bindings/wifi/nordic,nrf7001-qspi.yaml
     - dts/bindings/wifi/nordic,nrf7001-spi.yaml
+    - dts/bindings/wifi/nordic,nrf7120-wifi.yaml
     - boards/shields/nrf7002ek/
   labels:
     - "area: Wi-Fi"

boards/nordic/nrf7120dk/Kconfig.defconfig

@@ -0,0 +1,36 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+config HW_STACK_PROTECTION
+	default ARCH_HAS_STACK_PROTECTION
+
+if BOARD_NRF7120DK_NRF7120_CPUAPP
+
+config HAS_BT_CTLR
+	default BT
+
+config ROM_START_OFFSET
+	default 0x800 if BOOTLOADER_MCUBOOT
+
+endif # BOARD_NRF7120DK_NRF7120_CPUAPP
+
+if BOARD_NRF7120DK_NRF7120_CPUAPP_NS
+
+config BOARD_NRF7120DK
+	select USE_DT_CODE_PARTITION
+
+config HAS_BT_CTLR
+	default BT
+
+# By default, if we build for a Non-Secure version of the board,
+# enable building with TF-M as the Secure Execution Environment.
+config BUILD_WITH_TFM
+	default y
+
+# By default, if we build with TF-M, instruct build system to
+# flash the combined TF-M (Secure) & Zephyr (Non Secure) image
+config TFM_FLASH_MERGED_BINARY
+	default y
+	depends on BUILD_WITH_TFM
+
+endif # BOARD_NRF7120DK_NRF7120_CPUAPP_NS

boards/nordic/nrf7120dk/Kconfig.nrf7120dk

@@ -0,0 +1,7 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+config BOARD_NRF7120DK
+	select SOC_NRF7120_ENGA_CPUAPP if BOARD_NRF7120DK_NRF7120_CPUAPP || \
+		BOARD_NRF7120DK_NRF7120_CPUAPP_NS
+	select SOC_NRF7120_ENGA_CPUFLPR if BOARD_NRF7120DK_NRF7120_CPUFLPR || \
+		BOARD_NRF7120DK_NRF7120_CPUFLPR_XIP

boards/nordic/nrf7120dk/board.cmake

@@ -0,0 +1,20 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_SOC_NRF7120_ENGA_CPUAPP)
+  board_runner_args(jlink "--device=cortex-m33" "--speed=4000")
+elseif(CONFIG_SOC_NRF7120_ENGA_CPUFLPR)
+  board_runner_args(jlink "--speed=4000")
+endif()
+
+if(BOARD_NRF7120DK_NRF7120_CPUAPP_NS)
+  set(TFM_PUBLIC_KEY_FORMAT "full")
+endif()
+
+if(CONFIG_TFM_FLASH_MERGED_BINARY)
+  set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex)
+endif()
+
+include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/nordic/nrf7120dk/board.yml

@@ -0,0 +1,10 @@
+board:
+  name: nrf7120dk
+  vendor: nordic
+  socs:
+  - name: nrf7120
+    variants:
+    - name: xip
+      cpucluster: cpuflpr
+    - name: ns
+      cpucluster: cpuapp

boards/nordic/nrf7120dk/doc/index.rst

@@ -0,0 +1,103 @@
+.. zephyr:board:: nrf7120dk
+
+Overview
+********
+
+The nRF7120 Development Kit hardware provides support for the Nordic Semiconductor
+nRF7120 Arm Cortex-M33 CPU and the following devices:
+
+* :abbr:`SAADC (Successive Approximation Analog to Digital Converter)`
+* CLOCK
+* :abbr:`GPIO (General Purpose Input Output)`
+* :abbr:`TWIM (I2C-compatible two-wire interface master with EasyDMA)`
+* MEMCONF
+* :abbr:`MPU (Memory Protection Unit)`
+* MRAM
+* MSPI
+* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
+* :abbr:`PWM (Pulse Width Modulation)`
+* :abbr:`GRTC (Global real-time counter)`
+* Segger RTT (RTT Console)
+* :abbr:`SPI (Serial Peripheral Interface)`
+* :abbr:`UARTE (Universal asynchronous receiver-transmitter)`
+* :abbr:`WDT (Watchdog Timer)`
+
+Hardware
+********
+
+nRF7120 DK has two crystal oscillators:
+
+* High-frequency 64 MHz crystal oscillator (HFXO)
+* Low-frequency 32.768 kHz crystal oscillator (LFXO)
+
+The crystal oscillators can be configured to use either
+internal or external capacitors.
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Applications for the ``nrf7120dk/nrf7120/cpuapp`` board target can be
+built, flashed, and debugged in the usual way. See
+:ref:`build_an_application` and :ref:`application_run` for more details on
+building and running.
+
+Applications for the ``nrf7120dk/nrf7120/cpuflpr`` board target need
+to be built using sysbuild to include the ``vpr_launcher`` image for the application core.
+
+Enter the following command to compile ``hello_world`` for the FLPR core:
+
+.. code-block:: console
+
+   west build -p -b nrf7120dk/nrf7120/cpuflpr --sysbuild
+
+
+Flashing
+========
+
+As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world`
+application.
+
+.. warning::
+
+   When programming the device, you might get an error similar to the following message::
+
+    ERROR: The operation attempted is unavailable due to readback protection in
+    ERROR: your device. Please use --recover to unlock the device.
+
+   This error occurs when readback protection is enabled.
+   To disable the readback protection, you must *recover* your device.
+
+   Enter the following command to recover the core::
+
+    west flash --recover
+
+   The ``--recover`` command erases the flash memory and then writes a small binary into
+   the recovered flash memory.
+   This binary prevents the readback protection from enabling itself again after a pin
+   reset or power cycle.
+
+Follow the instructions in the :ref:`nordic_segger` page to install
+and configure all the necessary software. Further information can be
+found in :ref:`nordic_segger_flashing`.
+
+To build and program the sample to the nRF7120 DK, complete the following steps:
+
+First, connect the nRF7120 DK to you computer using the IMCU USB port on the DK.
+Next, build the sample by running the following command:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: nrf7120dk/nrf7120/cpuapp
+   :goals: build flash
+
+Testing the LEDs and buttons in the nRF7120 DK
+************************************************
+
+Test the nRF7120 DK with a :zephyr:code-sample:`blinky` sample.

boards/nordic/nrf7120dk/nrf7120_cpuapp_common.dtsi

@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* This file is common to the secure and non-secure domain */
+
+#include "arm/nordic/nrf7120_enga_cpuapp.dtsi"
+#include "nrf7120dk_nrf7120-common.dtsi"
+
+/ {
+	chosen {
+		zephyr,console = &uart30;
+		zephyr,shell-uart = &uart30;
+		zephyr,uart-mcumgr = &uart30;
+		zephyr,bt-mon-uart = &uart30;
+		zephyr,bt-c2h-uart = &uart30;
+		zephyr,flash = &cpuapp_mram;
+		zephyr,ieee802154 = &ieee802154;
+		zephyr,wifi = &wlan0;
+	};
+
+	/* TODO: Fine tune the sizes */
+	ipc_shm_area_cpuapp_cpuuma: memory@200C0000 {
+		compatible = "mmio-sram";
+		reg = <0x200C0000 0x2000>;
+		ranges = <0x0 0x200C0000 0x2000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		status = "okay";
+
+		ipc_shm_cpuapp_cpuuma_0: memory@0 {
+			reg = <0x0 DT_SIZE_K(2)>;
+		};
+
+		ipc_shm_cpuuma_cpuapp_0: memory@800 {
+			reg = <0x800 DT_SIZE_K(2)>;
+		};
+
+		ipc_shm_cpuapp_cpuuma_1: memory@1000 {
+			reg = <0x1000 DT_SIZE_K(2)>;
+		};
+
+		ipc_shm_cpuuma_cpuapp_1: memory@1800 {
+			reg = <0x1800 DT_SIZE_K(2)>;
+		};
+	};
+
+	ipc {
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-icmsg";
+			tx-region = <&ipc_shm_cpuapp_cpuuma_0>;
+			rx-region = <&ipc_shm_cpuuma_cpuapp_0>;
+			mboxes = <&wifi_bellboard 2>,
+				 <&cpuapp_bellboard 0>;
+			mbox-names = "tx", "rx";
+			status = "okay";
+		};
+
+		ipc1: ipc1 {
+			compatible = "zephyr,ipc-icmsg";
+			tx-region = <&ipc_shm_cpuapp_cpuuma_1>;
+			rx-region = <&ipc_shm_cpuuma_cpuapp_1>;
+			mboxes = <&wifi_bellboard 3>,
+				 <&cpuapp_bellboard 1>;
+			mbox-names = "tx", "rx";
+			status = "okay";
+		};
+	};
+};
+
+&cpuapp_sram {
+	status = "okay";
+};
+
+&grtc {
+	owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+	/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
+	child-owned-channels = <3 4 7 8 9 10 11>;
+	status = "okay";
+};
+
+&uart30 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpiote20 {
+	status = "okay";
+};
+
+&gpiote30 {
+	status = "okay";
+};
+
+&radio {
+	status = "okay";
+};
+
+&ieee802154 {
+	status = "okay";
+};
+
+&temp {
+	status = "okay";
+};
+
+&clock {
+	status = "okay";
+};
+
+&spi00 {
+	status = "okay";
+	cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&spi00_default>;
+	pinctrl-1 = <&spi00_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&adc {
+	status = "okay";
+};
+
+&pwr_antswc {
+	status = "okay";
+};
+
+&wifi {
+	status = "okay";
+};
+
+&audio_auxpll {
+	nordic,frequency = <NRF_AUXPLL_FREQ_DIV_AUDIO_48K>;
+	status = "okay";
+};
+
+&cpuapp_bellboard {
+	status = "okay";
+};
+
+&wifi_bellboard {
+	status = "okay";
+};
+
+&qspi00 {
+	status = "okay";
+	op-mode = "MSPI_OP_MODE_CONTROLLER";
+};