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feat: Add minimum simulation time warnings to testbenches VUnit Tests #32: Commit 45eae77 pushed by nselvara
1m 1s v1.2.3
v1.2.3
1m 1s
feat: Add minimum simulation time warnings to testbenches VUnit Tests #31: Commit 45eae77 pushed by nselvara
1m 4s main
main
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docs: Add Xilinx library warnings to README and test_runner VUnit Tests #30: Commit 088f905 pushed by nselvara
1m 2s main
main
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docs: Add Xilinx library warnings to README and test_runner VUnit Tests #29: Commit 088f905 pushed by nselvara
1m 5s v1.2.2
v1.2.2
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docs: Add Xilinx library warnings to README and test_runner VUnit Tests #28: Commit 088f905 pushed by nselvara
1m 15s spi_multiword
spi_multiword
1m 15s
spi: Allow multi-word transfer via FIFO VUnit Tests #27: Commit 8e39bb7 pushed by nselvara
1m 15s spi_multiword
spi_multiword
1m 15s
spi: Moved testbenches VUnit Tests #23: Commit e500d4a pushed by nselvara
1m 3s main
main
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spi: Refactor alignment processes for serial data output and chip sel… VUnit Tests #22: Commit 93b45b2 pushed by nselvara
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pll: Bugfix - Covert ps to ns VUnit Tests #21: Commit 1770df6 pushed by nselvara
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spi: Add configurable parameters for chip count and data width in ord… VUnit Tests #19: Commit 36f986b pushed by nselvara
3m 4s main
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spi: Bugfix - Only one chip should be active VUnit Tests #18: Commit ba9c1ab pushed by nselvara
2m 4s v1.2.1
v1.2.1
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ci/cd: Recreate Unisim/Xilinx library if VHDL is available VUnit Tests #17: Commit cddb204 pushed by nselvara
1m 55s v1.2.0
v1.2.0
1m 55s
VUnit Tests VUnit Tests #14: by nselvara
2m 10s v1.0.0
v1.0.0
2m 10s
spi: Bugfix - Only one chip should be active VUnit Tests #13: Commit ba9c1ab pushed by nselvara
1m 33s main
main
1m 33s
async_fifo: Fixed colours of texts and positioned the texts above the… VUnit Tests #12: Commit 9e9e996 pushed by nselvara
1m 50s main
main
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ci/cd: Recreate Unisim/Xilinx library if VHDL is available VUnit Tests #11: Commit cddb204 pushed by nselvara
1m 9s main
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1m 9s
feat: Add test report generation and update CI/CD test runner for xun… VUnit Tests #3: Commit 9ee8b1e pushed by nselvara
1m 24s main
main
1m 24s
Add VHDL-Utils as submodule in ip/vhdl_utils VUnit Tests #2: Commit 3675865 pushed by nselvara
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main
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