Add FADT table support

[CookieComputing]

Add the FADT table to stage0, and make sure that we can parse it.

Referencing the UEFI spec, we should always expect an FADT to be present:

As shown in Description Table Structures , there is always a physical address in the Root System Description Table for the Fixed ACPI Description Table (FADT).

For logs, take a look at:

fadt_logs.txt

The most important part of these logs, coming from one of our machines:

stage0 INFO: FADT: Fadt { header: DescriptionHeader { signature: [70, 65, 67, 80], length: 244, revision: 3, checksum: 145, oem_id: [66, 79, 67, 72, 83, 32], oem_table_id: [66, 88, 80, 67, 32, 32, 32, 32], oem_revision: 1, creator_id: 1129338946, creator_revision: 1 }, firmware_ctrl: 1072693248, dsdt_address: 1072693312, _reserved1: 1, preferred_power_management_profile: 0, sci_interrupt: 9, sci_command_port_address: 0, acpi_enable: 0, acpi_disable: 0, s4bios_req: 0, pstate_control: 0, pm1a_event_block: 0, pm1b_event_block: 0, pm1a_control_block: 4, pm1b_control_block: 0, pm2_control_block: 0, pm_timer_block: 8, general_purpose_event0_block: 32, general_purpose_event1_block: 0, pm1_event_len: 4, pm1_control_len: 2, pm2_control_len: 0, pm_timer_len: 4, general_purpose_event0_len: 16, general_purpose_event1_len: 0, general_purpose_event1_base: 0, cstate_control: 0, worst_c2_latency: 4095, worst_c3_latency: 4095, flush_size: 0, flush_stride: 0, duty_offset: 0, duty_width: 0, day_alarm: 0, month_alarm: 0, century: 50, iapc_boot_arch_flags: 2, _reserved2: 0, fixed_feature_flags: 33957, reset_register: GenericAddressStructure { address_space: 1, bit_width: 8, bit_offset: 0, access_size: 0, address: 3321 }, reset_value: 15, arm_boot_arch_flags: 0, fadt_minor_version: 0, extended_firmware_control: 0, extended_dsdt_address: 1072693312, extended_pm1a_event_block: GenericAddressStructure { address_space: 1, bit_width: 32, bit_offset: 0, access_size: 0, address: 0 }, extended_pm1b_event_block: GenericAddressStructure { address_space: 0, bit_width: 0, bit_offset: 0, access_size: 0, address: 0 }, extended_pm1a_control_block: GenericAddressStructure { address_space: 1, bit_width: 16, bit_offset: 0, access_size: 0, address: 4 }, extended_pm1b_control_block: GenericAddressStructure { address_space: 0, bit_width: 0, bit_offset: 0, access_size: 0, address: 0 }, extended_pm2_control_block: GenericAddressStructure { address_space: 0, bit_width: 0, bit_offset: 0, access_size: 0, address: 0 }, extended_pm_timer_block: GenericAddressStructure { address_space: 1, bit_width: 32, bit_offset: 0, access_size: 0, address: 8 }, extended_general_purpose_event0_block: GenericAddressStructure { address_space: 1, bit_width: 128, bit_offset: 0, access_size: 0, address: 32 }, extended_general_purpose_event1_block: GenericAddressStructure { address_space: 0, bit_width: 0, bit_offset: 0, access_size: 0, address: 0 }, sleep_control_register: GenericAddressStructure { address_space: 65, bit_width: 80, bit_offset: 73, access_size: 67, address: 5711207554692939920 }, sleep_status_register: GenericAddressStructure { address_space: 67, bit_width: 72, bit_offset: 83, access_size: 32, address: 2314885531408816194 }, hypervisor_vendor_identity: 4850473839169110017 }
stage0 INFO: Entry APIC (0x3ff022de-0x3ff0236e): DescriptionHeader { signature: [65, 80, 73, 67], length: 144, revision: 3, checksum: 73, oem_id: [66, 79, 67, 72, 83, 32], oem_table_id: [66, 88, 80, 67, 32, 32, 32, 32], oem_revision: 1, creator_id: 1129338946, creator_revision: 1 }

I think CI should verify that this builds on stage0 infra? For various reasons I don't have access to an x86 box that I can test with the OSS setup right now, but I think it should build and launch fine