To do the assignment 1, you must specify what commit hash of the Arch project that you will be writing your assignment against. If you choose to accept Chris's original proposal unchanged, that is sufficient to finish the assignment.
However, there were many valid points brought up in discussion on Thursday that you should consider. To organize this discussion so that you can have a final proposal which is a reasonable substrate for future projects.
Relatively conservative ISAs which are probably good source material in no particular order.
- 6502
- 8080/z80 ← a really classic 16 bit ISA
- PDP11
- CDC6000
- MIPS
- ARM
- PowerPC
- Amtel AVR ← a classic in order 8 bit ISA
- SuperH
- Motorola 6800
- 8086
- 80386 ← the granddaddy of x86_64
- IBM360
The master branch will not track any single proposal. If you have a suggestion for an ISA, please either fork one of the existing proposals onto a new branch or create a new branch based off of master replacing the README file with whatever you may find appropriate as an introduction and explicitly addressing Dr. Gheith's ISA usability questions:
- what is the word size?
- what is the instruction layout?
- do you have any special registers?
- how do we do function calls?
- how many register file read/write ports (maximum number of registers read / written per cycle)?
- how many memory read/write ports?
- how do we implement arrays / structures / pointers / function pointers?
- how do we implement control structures: if / while / switch?
- how do you implement the stack?
- how easy is it to detect / resolve inter-instruction dependencies
- how easy is it to identify operations / operands
- how easy is it to identify branch targets
- implicit vs. explicit operands / coupling
The following questions are also legitimate.
- how do you implement integer overflow/underflow and "exception" detection?
- how do you implement virtual memory?
- do you have privileged instructions? memory regions? how is privilege tracked?
Note that the Batbridge specification does not address these questions. As you will need to implement this instruction set yourselves in what approximates hardware I advise against investing much energy in these questions as they are not critical to the instruction scheduling problems which will dominate this course.
As a courtesy to other authors, please send pull requests to proposals that are not your own rather than directly contributing.
Dr. Gheith or I will update and version the master branch when a
proposal is decided on. Until then please don't touch it.