This project is the homework from NTHU CS Computer Architecture course by Ren-Song Tsay.
1.In first project, we implement a single-cycle, functional processor simulator according to the reduced MIPS R3000 ISA.
2.In second project, we implement a pipelined, functional processor simulator for the reduced MIPS R3000 ISA, following the specification “Datasheet for the Reduced MIPS R3000 ISA”