Implement S_CMD_S_PIN_STATE command

[dan-corneanu]

I have an FPGA dev board that has a flash SPI chip. Besides MISO, MOSI, SCK and CS pins it also has a CREST pin that needs to be driven low when you access the flash chip. Currently I have to manually ground CRESET every time I upload a new image to the flash chip.

I thought, I could take advantage of the S_CMD_S_PIN_STATE cmd and drive the CREST pin low on Output drivers enabled and high on Output drivers disabled.

I've implemented some code to handle the S_CMD_S_PIN_STATE cmd. However, the CREST pin (connected to GP5) does not toggle as expected. Could someone please have a look and tell me if I have missed something?

[dan-corneanu]

@nezza @kazigk
Could one of you please have a look at this implementation of S_CMD_S_PIN_STATE and let me know what is wrong with it?

[kazigk]

@dan-corneanu Sorry, just noticed your mention 😅

I just read through the serprog docs as well as the implementation in flashrom, and your code looks correct to me.
Try adding a little delay after you put that pin low (and before sending ACK), maybe it needs a few machine cycles to process 😉

[dan-corneanu]

@kazigk why did you use a PIO implementation of SPI instead of using one of the hardware SPI peripherals?

[dan-corneanu]

Coming back to this, after a long break, I am not able to reproduce the issue anymore. Most probably it was related to some electrical fault. I can confirm that CREST does work as expected and I am able to read and write the flash chip on my FPGA board.

I have done a bit of refactoring to move the output_drivers_disable/enable functionality to its own set of functions and to fully release all the pins on output_drivers_disable. This way someone else can control them after flashrom is done.

I am not sure if CREST makes any sense for your project, but if you find the rest of the refactoring useful I am happy to submit a clean PR excluding the CREST related code. Otherwise please feel free to close this one.