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standanley wants to merge 93 commits into
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Combine branches #4

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@standanley standanley commented Mar 4, 2020

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@standanley
Quick fix adding the minimum amount of code to get the functionality …
3dfc51d 
…I need
@standanley
Fixed style in new test
8c92eb0
@standanley
Fix indexing into one bit of a spice bus
e744e1e
@standanley
Merge pull request #1 from standanley/spice_bus_indexing
e72dda3 
Fix indexing into one bit of a spice bus
@standanley
Merge remote-tracking branch 'upstream/master'
deaea62
@standanley
Wrote background poke Thread class
311d6d3
@standanley
Finished writing background poke interleaving but have not even run i…
26a0eb4 
…t yet
@standanley
I think it is working for spice targets.
0368670
@standanley
Working on tests for background pokes
95ddd0b
@standanley
Changed location of unit conversion in spice_target
794d7a3
@standanley
Added Print action and nothing more
2ff5d92
@standanley
Added read to VerilogTarget but no implementation
5276903
@standanley
Reading now works for systemverilog targets
7c94e67
@standanley
Reads work for spice too, based on minimal testing
78abb7c
@standanley
Edge finder is now working. Need to clean up prints
64bd264
@standanley
Allow indexing into spice buses
6198fa2
@standanley
Phase measurement now working in spice
e5f9ecb
@standanley
Deleted some debugging prints
6a61712
@standanley
Fixed bug in phase measurement and added test
4272bb4
@standanley
Merged spice_timing into read_action but some of the read_action test…
8a23678 
…s are broken
@standanley
Changed background poke so it would not break spice reads. Still an i…
35faadf 
…ssue with verilog reads
@standanley
Fixed default clock step
893c859
@standanley
Fixed bug with clocks in background_poke
7aa57ff
@standanley
Changed pwc to pwl conversion to allow two points within rt of each o…
bfeba86 
…ther
@standanley
Changed spice_target to print stderr of simulation command
2dc8063
@standanley
Marked read action as not implemented in verilator_target
ae39e7a
@standanley
Bugfix and labeling of error output.
a6542d0
@standanley
New read styles, decreased default step size in spice transient sim
4939b87
@standanley
fixed issue with block reads beyond the end of simulation time
096a74f
@standanley
Got rid of some references to old style read using save_for_later. St…
657e003 
…ill need to fix tests, but will wait until after merge
sgherbst and others added 30 commits March 13, 2020 02:01
@sgherbst
fix deprecation warning
7b92980
@sgherbst
Merge pull request leonardt#225 from leonardt/top_module
87616e7 
Implement top_module for all SystemVerilogTargets
@sgherbst
add support for paths with spaces to vivado
27e4878
@sgherbst
fix handling of define macros with quotes
246f2bf
@sgherbst
Merge pull request leonardt#226 from leonardt/paths_w_spaces_2
f8bd31e 
Fix minor bugs in Vivado TCL generation
@sgherbst
Release 3.0.9
aeb708e
@leonardt
Merge pull request leonardt#227 from leonardt/v_3_0_9
8742203 
Release 3.0.9
@standanley
Tiny change to avoid mantle comparison that broke on bit type
cfa3237
@standanley
First pass of understanding mLingua waveforms
30e621b
@standanley
Working on get_value in different domains. I think it works for syste…
f944500 
…mverilog, but I broke functionality for spice. Have a lingering TODO to force a wave dump on certain nodes when global waveform dumping is turned off
@standanley
Fix domain read for spice. Still some pending todos
0f0f90b
@standanley
Can now read frequency/phase with systemverilog target
84edb56
@standanley
Fixed a couple bugs in background poke
d0e7dad
@standanley
Edge find bug fix
eb22b9a
@standanley
Edge find bug fix
417361d
@standanley
Merge branch 'combine_branches' of https://github.com/standanley/fault …
bf34111 
…into combine_branches
@standanley
Fix tiny bug with recent changes
49ab608
@leonardt
Insert flags before other command options
3af3399
@leonardt
Initial clocks to zero
7e9d190
@leonardt
Update tests
a874eb2
@leonardt
Merge pull request leonardt#229 from leonardt/init-clock-zero
732729a 
Initial clocks to zero
@leonardt
Merge pull request leonardt#228 from leonardt/flags-order
02d746a 
Insert flags before other command options
@leonardt
Release 3.0.10
f98beb7
@standanley
Merged in master
ce9ae41
@standanley
Add flatten method to real_type
a62a3b4
@standanley
Merge branch 'add_flatten' into combine_branches
686b158
@standanley
Delete traces of old Read action (replaced by GetValue)
7c5fe10
@standanley
Fix floating point equality comparison
a255b2c
@standanley
Fixes for arrays of analog and outputs that are arrays
b921caa
@standanley
Slight update to verilog_target for domain_read
f990113
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5 participants

@standanley @sgherbst @leonardt @cdonovick