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Fix right shifts and sltu[i] instructions #8

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Fix right shifts and sltu[i] instructions #8

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b5d0737
Fix right shifts and sltu[i] instructions
Kristopher38 Jul 23, 2022
5180f0c
Fix JALR, make memory deterministic, add support for halfword stores …
Kristopher38 May 16, 2025
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19 changes: 10 additions & 9 deletions riscvmodel/insn.py
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Original file line number Diff line number Diff line change
Expand Up @@ -36,8 +36,9 @@ def execute(self, model: Model):
@isa("jalr", RV32I, opcode=0b1100111, funct3=0b000)
class InstructionJALR(InstructionIType):
def execute(self, model: Model):
target = (model.state.intreg[self.rs1] + self.imm) & 0xFFFFFFFE
model.state.intreg[self.rd] = model.state.pc + 4
model.state.pc = model.state.intreg[self.rs1] + self.imm
model.state.pc = target


@isa("beq", RV32I, opcode=0b1100011, funct3=0b000)
Expand Down Expand Up @@ -163,7 +164,7 @@ def execute(self, model: Model):
@isa("sltiu", RV32I, opcode=0b0010011, funct3=0b011)
class InstructionSLTIU(InstructionIType):
def execute(self, model: Model):
if model.state.intreg[self.rs1].unsigned() < int(self.imm):
if model.state.intreg[self.rs1].unsigned() < int(self.imm) & 0xFFFFFFFF:
model.state.intreg[self.rd] = 1
else:
model.state.intreg[self.rd] = 0
Expand Down Expand Up @@ -203,7 +204,7 @@ def execute(self, model: Model):
@isa("srai", RV32I, opcode=0b0010011, funct3=0b101, funct7=0b0100000)
class InstructionSRAI(InstructionISType):
def execute(self, model: Model):
model.state.intreg[self.rd] = model.state.intreg[self.rs1] >> self.shamt
model.state.intreg[self.rd] = (model.state.intreg[self.rs1] & 0xFFFFFFFF) >> self.shamt


@isa("add", RV32I, opcode=0b0110011, funct3=0b000, funct7=0b0000000)
Expand Down Expand Up @@ -236,12 +237,12 @@ def execute(self, model: Model):

@isa("sltu", RV32I, opcode=0b0110011, funct3=0b011, funct7=0b0000000)
class InstructionSLTU(InstructionRType):
def execute(self, state: State):
if state.intreg[self.rs1].unsigned() < state.intreg[
def execute(self, model: Model):
if model.state.intreg[self.rs1].unsigned() < model.state.intreg[
self.rs2].unsigned():
state.intreg[self.rd] = 1
model.state.intreg[self.rd] = 1
else:
state.intreg[self.rd] = 0
model.state.intreg[self.rd] = 0


@isa("xor", RV32I, opcode=0b0110011, funct3=0b100, funct7=0b0000000)
Expand All @@ -253,8 +254,8 @@ def execute(self, model: Model):
@isa("srl", RV32I, opcode=0b0110011, funct3=0b101, funct7=0b0000000)
class InstructionSRL(InstructionRType):
def execute(self, model: Model):
src = model.state.intreg[self.rs1]
shift = model.state.intreg[self.rs2] & 0x1f
src = model.state.intreg[self.rs1].unsigned()
shift = int(model.state.intreg[self.rs2] & 0x1f)
model.state.intreg[self.rd] = src >> shift


Expand Down
2 changes: 1 addition & 1 deletion riscvmodel/isa.py
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Original file line number Diff line number Diff line change
Expand Up @@ -331,7 +331,7 @@ def __str__(self) -> str:

class InstructionILType(InstructionIType, metaclass=ABCMeta):
"""
I-type instruction specialization for stores. The produce a different
I-type instruction specialization for loads. They produce a different
assembler than the base class

:param rd: Destination register
Expand Down
14 changes: 9 additions & 5 deletions riscvmodel/model.py
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Original file line number Diff line number Diff line change
Expand Up @@ -79,20 +79,20 @@ def lb(self, address):
word = address >> 2
offset = address % 4
if word not in self.memory:
self.memory[word] = randrange(0, 1 << 32)
return 0
return (self.memory[word] >> (offset*8)) & 0xff

def lh(self, address):
word = address >> 2
offset = (address >> 1) % 2
if word not in self.memory:
self.memory[word] = randrange(0, 1 << 32)
return (self.memory[word] >> (offset*16)) & 0xffff
return 0
return (self.memory[word] >> (offset*16)) & 0xffff

def lw(self, address):
word = address >> 2
if word not in self.memory:
self.memory[word] = randrange(0, 1 << 32)
return 0
return self.memory[word]

def sb(self, address, data):
Expand All @@ -112,12 +112,16 @@ def commit(self):
address = update.addr
base = address >> 2
offset = address & 0x3
offset_hw = address & 0x2
if base not in self.memory:
self.memory[base] = randrange(0, 1 << 32)
self.memory[base] = 0
data = update.data
if update.gran == TraceMemory.GRANULARITY.BYTE:
mask = ~(0xFF << (offset*8)) & 0xFFFFFFFF
data = (self.memory[base] & mask) | (data << (offset*8))
elif update.gran == TraceMemory.GRANULARITY.HALFWORD:
mask = ~(0xFFFF << (offset_hw*8)) & 0xFFFFFFFF
data = (self.memory[base] & mask) | (data << (offset_hw*8))
self.memory[base] = data

self.memory_updates = []
Expand Down
5 changes: 2 additions & 3 deletions riscvmodel/types.py
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Original file line number Diff line number Diff line change
Expand Up @@ -226,11 +226,10 @@ def __lshift__(self, other):

def __rshift__(self, other):
new = Register(self.bits)
value = (self.value + 2**self.bits) if self.value < 0 else self.value
if isinstance(other, int):
new.set(value >> other)
new.set(self.value >> other)
elif isinstance(other, (Register, Immediate)):
new.set(value >> other.value)
new.set(self.value >> other.value)
else:
raise TypeError("unsupported operand type for Register >>: {}".format(other.__class__))
return new
Expand Down