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RISC-V fixes #6007
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RISC-V fixes #6007
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Thank you for the PR, generally speaking, LGTM.
I would like to see a full support of the rv32 target with LLVM - do you know what's missing on top of this pull request? Btw. can one test |
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For our case, the only remaining work to support rv32, is merely enabling it in this file. And I don't believe you can test |
All right, then include it in this PR so that it's a self-contained set of changes. And note I added a couple of relocations in the #6020 PR. This PR needs to be rebased.
Frankly speaking, we can definitely add |
This commit contains several RISC-V fixes we've accumulated: * Handle more RISC-V allocations * Metadata must be aligned by 8 * Pass pointer width instead of hardcoding it to 8 It fixes problems using wasmer in rv32, but for now the code does not aim to enable rv32. I feel like it is a bigger decision.
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This is rebased, I've also tweaked LLVM compiler's config to introduce rv32 targets.
I totally agree that a real board can never be replaced in many tests, e.g., performance analysis. But if we are limiting the goal to correctness testing, I personally believe qemu-user package can be quite handy. In addition, I would recommend having an environment where the host is 64-bit and the target is 32-bit, it helps uncover certain types of bugs, where pointer size of the host platform is used for target code. |
Great, please rename the PR as it's now purely about the
Speaking about the qemu cross compilation - we inherently need to have a cross LLVM binaries (something like https://github.com/mean00/LLVM-embedded-toolchain-for-rv32). Do you have any experience with that? I am all ears! |
This commit contains several RISC-V fixes we've accumulated:
It fixes problems using wasmer in rv32, but for now the code does not aim to enable rv32. I feel like it is a bigger decision.