This is the Hydra microprocessor architecture, developed as part of the ongoing project of development of a complete computational system for the Computational Systems Laboratories signatures of the Computer Engineering course at UNIFESP. This architecture was developed using the Verilog HDL language and the Quartus Prime 16.1 software, and it has been tested in Altera DE2-115 board.
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C- minus compiler for the Hydra microprocessor architecture
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