SIPO-register

LabVIEW project for Digital Logic Design course (EEC242).

Name		Name	Last commit message	Last commit date
Latest commit History 9 Commits
.gitattributes		.gitattributes
And3 14.vi		And3 14.vi
And3 15.vi		And3 15.vi
And3 16.vi		And3 16.vi
And3 17.vi		And3 17.vi
And3.vit		And3.vit
CLK.vi		CLK.vi
D_FlipFlop 1-1.vi		D_FlipFlop 1-1.vi
D_FlipFlop 2-1.vi		D_FlipFlop 2-1.vi
D_FlipFlop 3-1.vi		D_FlipFlop 3-1.vi
D_FlipFlop 4-1.vi		D_FlipFlop 4-1.vi
D_FlipFlop.vit		D_FlipFlop.vit
D_FlipFlopWithReset 14.vi		D_FlipFlopWithReset 14.vi
D_FlipFlopWithReset 15.vi		D_FlipFlopWithReset 15.vi
D_FlipFlopWithReset 16.vi		D_FlipFlopWithReset 16.vi
D_FlipFlopWithReset 17.vi		D_FlipFlopWithReset 17.vi
D_FlipFlopWithReset.vit		D_FlipFlopWithReset.vit
Nand3 14.vi		Nand3 14.vi
Nand3 15.vi		Nand3 15.vi
Nand3 16.vi		Nand3 16.vi
Nand3 17.vi		Nand3 17.vi
Nand3.vit		Nand3.vit
README.md		README.md
SIPO register.aliases		SIPO register.aliases
SIPO register.lvlps		SIPO register.lvlps
SIPO register.lvproj		SIPO register.lvproj
SIPO.vi		SIPO.vi
SIPO_Present_CLR.vi		SIPO_Present_CLR.vi

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