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Kirann260/README.md

Hi, I'm Kiran Meena

  • Verilog, Digital Design & RISC-V Enthusiast
  • FPGA + simulation practice (Vivado, EDA Playground)
  • Currently contributing to open-source RISC-V projects
  • Goal: LFX RISC-V Mentorship (Jan Session)
  • Email: bee_2023022@iiitm.ac.in Check my contributions → riscv-contributions

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  1. Kirann260 Kirann260 Public

    1

  2. riscv-contributions riscv-contributions Public

    1

  3. serv serv Public

    Forked from olofk/serv

    SERV - The SErial RISC-V CPU

    Verilog 1

  4. single-cycle-riscv-processor single-cycle-riscv-processor Public

    My "Single Cycle RISC-V Processor" project in Vivado

    Verilog 1

  5. ARM_CPU_Design ARM_CPU_Design Public

    Verilog

  6. synchronous-fifo synchronous-fifo Public

    Verilog 1