Overview
This project implements an ARM-style CPU using Verilog HDL. The design includes core CPU components such as ALU, controller, register file, datapath, instruction memory, and data memory. The goal of this project is to understand CPU microarchitecture and RTL-level design using a modular approach.
This implementation is intended for educational and learning purposes.
Features
- Modular RTL design using Verilog
- Arithmetic and Logic Unit (ALU)
- Register File with general-purpose registers
- Instruction Fetch, Decode, Execute, Memory, and Writeback stages
- Load and Store operations
- Branch instruction support
- Clean separation of datapath and control logic
Directory Structure
ARM_CPU_Design/
├── arm_cpu_rtl/ # RTL Verilog source files
├── tb/ # SystemVerilog testbench
├── sim/ # Simulation waveform images
└── README.md
Verification
The CPU was verified using a SystemVerilog testbench in Xilinx Vivado. The simulation confirms correct instruction execution, data flow, and control signal behavior.
Tools Used
- Verilog / SystemVerilog
- Xilinx Vivado
- Git & GitHub
Future Improvements
- Add pipeline support
- Implement hazard detection and forwarding
- Support more ARM instructions
- Improve testbench coverage with assertions