fix clk_wiz divisor calculation #356
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Added VEK385 HDMI2.1 Example Design support Signed-off-by: S Shreesh <s.shreesh@amd.com>
update Embedded SW license Signed-off-by: Manikanta Sreeram <manikanta.sreeram@amd.com> Acked-by: Addepalli, Siva <siva.addepalli@amd.com>
Added I2C reset in IDT GetRegister and SetRegister functions Signed-off-by: S Shreesh <s.shreesh@amd.com> Acked-for-series: Kalyanchakravathy Podalakuri <kalyanchakravathy.podalakuri@amd.com>
Added I2C reset in IDT GetRegister and SetRegister functions Signed-off-by: S Shreesh <s.shreesh@amd.com> Acked-for-series: Kalyanchakravathy Podalakuri <kalyanchakravathy.podalakuri@amd.com>
HMAC Key length can be of any length so updating the validation to check the max value with XASU_ASU_DMA_MAX_TRANSFER_LENGTH. Signed-off-by: Palakurthy Yogitha <palakurthy.yogitha@amd.com> Acked-by: Mounika Akula <mounika.akula@amd.com>
1) Updated the examples LookupConfig() API to use baseaddress for system device-tree flow. 2) Updated the interrupt example to use interrupt wrapper API for system device-tree flow. 3) Added example meta-data in the csudma.yaml inorder to populate examples under import examples section in the vitis new gui when this driver is pulled. Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com> Acked-for-series: Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
1) Updated the examples LookupConfig() API to use baseaddress for system device-tree flow. 2) Updated the interrupt example to use interrupt wrapper API for system device-tree flow. 3) Added example meta-data in the csudma.yaml inorder to populate examples under import examples section in the vitis new gui when this driver is pulled. 4) Update the YAML to generate xparameters.h defines in alignment with the XSCT flow by adding xparam_prefix and adding additionalProperties sections. Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com> Acked-for-series: Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
…gister Fix correct offset when reading INGRESS/EGRESS_CONTROL register. Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> Acked-by: Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
- The argument passed to XPmClock_GetByIdx should be the node index, not the array index. This adjustment improves function accuracy and prevents errors due to incorrect indexing. Signed-off-by: Trung tran <trung.tran@amd.com> Acked-by: Madhav Bhatt <madhav.bhatt@amd.com>
The patch fixes misra-c rule 17.12. Problem: MISRA C-2012 Functions (MISRA C-2012 Rule 17.12) 1. misra_c_2012_rule_17_12_violation: Function identifier PowerUp_OCM_BANK3 or similar function is not used to call the function or preceded by &. Solution: Added & symbol for the function identifier. Signed-off-by: Ronak Jain <ronak.jain@amd.com> Acked-for-series: Nicole Baze <amanda.baze@amd.com>
The patch fixes the misra-c rule 17.11. Problem: MISRA C-2012 Functions (MISRA C-2012 Rule 17.11) misra_c_2012_rule_17_11_violation: Function XPsmfw_ExceptionHandler declared without noreturn does not return. Solution: Added noreturn arrtribute. Signed-off-by: Ronak Jain <ronak.jain@amd.com> Acked-for-series: Nicole Baze <amanda.baze@amd.com>
…to extern c keyword The xdptxss_dp21_tx.h is edited at the end to rectify the closing of brace and #endif Signed-off-by: Nishant Dhonde <nishant.dhonde@amd.com> Acked-by: Kalyanchakravathy Podalakuri<kalyanchakravathy.podalakuri@amd.com>
Updated default eam error actions for APLL1 & RPUE fatal error Signed-off-by: Sreedhar Kundella <sreedhar.kundella@amd.com> Acked-by: Mounika Akula <mounika.akula@amd.com>
…e time When TEST_SAFE is asserted it will prevent correct read of PCSR CONTROL register. Due to this we are not able to read back PCSR CONTROL register during DAC/ADC SCAN_CLEAR_TRIGGER. So, write into TEST_SAFE and SCAN_CLEAR_TRIGGER at the same time. Signed-off-by: Sandeep Reddy Ghanapuram <sandeep.reddy-ghanapuram@amd.com> Acked-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
XilSKey_ZynqMp_EfusePs_Write_UsrCtrlBits is returning XST_FAILURE for a request to program user control eFuses which are already programmed. Update the XilSKey_ZynqMp_EfusePs_Write_UsrCtrlBits, to return XST_SUCCESS for the above case. Signed-off-by: Kalyani Akula <kalyani.akula@amd.com> Acked-by: Durga Challa <durga.challa@amd.com>
In the MIPI VCk190 application, 1080P resolution is hardcoded, even CSI can support for 4K capture. Signed-off-by: Dhanunjanrao Katta <katta.dhanunjanrao@amd.com> Acked-by: Gaddipati, Naveen <naveen.gaddipati@amd.com>
Call the user callback when there is a glitch in video ready input in TMDS mode. Signed-off-by: Rajesh Gugulothu <rajesh.gugulothu@amd.com>
Register video ready error callbacks. Signed-off-by: Rajesh Gugulothu <rajesh.gugulothu@amd.com>
Reset the clock detector module Rx path in GT controller when there is a glitch in the video ready input. Signed-off-by: Rajesh Gugulothu <rajesh.gugulothu@amd.com>
Reset the clock detector module Rx path in GT controller when there is a glitch in the video ready input. Signed-off-by: Rajesh Gugulothu <rajesh.gugulothu@amd.com>
- Add check PLATFORM_VERSION_COSIM where PLATFORM_VERSION_QEMU is checked. Signed-off-by: Trung tran <trung.tran@amd.com> amanda.baze@amd.com
I3C and MMI Reset are peripheral reset and not system reset. So fix their type and sub-class accordingly. Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com> Acked-by: Izhar Ameer Shaikh <izhar.ameer.shaikh@amd.com>
When the user wants to load image from any full pdi(other than boot pdi) which is stored in image store, PLM is not pointing to the correct metaheader offset and this causes image header table validation failure . Signed-off-by: Preethi Kolli <preethi.kolli@amd.com> Acked-by: Mounika Akula <mounika.akula@amd.com> Acked-by: Mounika Akula <mounika.akula@amd.com>
preserve the reverse data operation status and only overwrite it with the secure zeroize operation status if it's success. Signed-off-by: Nandanikhil Gajulapally <nandanikhil.gajulapally@amd.com> Acked-by: Kalyani Akula <kalyani.akula@amd.com>
Bootgen places IV's added in an encrypted bif in big endian format in PDI. XilNvm also programs the IV's into eFuses in big endian format. During SHWROT boot, in ROM IV criteria checks for PLM and DP IV's, ROM is expecting the IV's in LE format in eFuse. So, PLM and DP IV's need to be programmed in LE format to meet this criteria checks. This has already been taken care in xilnvm_efuse_versal_server_example.c But porting the same fix to xilnvm_efuse_versal_client_example.c was missed during initial Versal developement as client/server architecture was introduced later. Update the xilnvm_efuse_versal_client_example.c to program PLM and DP IV's in LE format. Signed-off-by: Kalyani Akula <kalyani.akula@amd.com> Acked-by: Durga Challa <durga.challa@amd.com>
Write in SCDC SET register before writing in CLR register to clear the SCDC buffer. Signed-off-by: Rajesh Gugulothu <rajesh.gugulothu@amd.com> Acked-for-series: Gaddipati, Naveen <naveen.gaddipati@amd.com>
Write in SCDC SET register before writing in CLR register to clear the SCDC buffer. Signed-off-by: Rajesh Gugulothu <rajesh.gugulothu@amd.com> Acked-for-series: Gaddipati, Naveen <naveen.gaddipati@amd.com>
…CKING checks in microblaze port The MicroBlaze FreeRTOS port does not support the portHAS_STACK_OVERFLOW_CHECKING feature. Therefore, the related checks should be removed, as enabling this feature expects different arguments for the pxPortInitialiseStack() API. Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com> Acked-by: Anirudha Sarangi <anirudha.sarangi@amd.com>
The patch fixes the misra-c rule 17.12 violation. MISRA C-2012 Functions (MISRA C-2012 Rule 17.12) 1. misra_c_2012_rule_17_12_violation: Function identifier is not used to call the function or preceded by &. Solution: Added & to the function identifier. Signed-off-by: Ronak Jain <ronak.jain@amd.com> Acked-for-series: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
The patch fixes the misra-c violation for 17.11 rule. Problem: MISRA C-2012 Functions (MISRA C-2012 Rule 17.11) misra_c_2012_rule_17_11_violation: Function XPfw_Exception_Handler declared without noreturn does not return. Solution: Added noreturn attribute Signed-off-by: Ronak Jain <ronak.jain@amd.com> Acked-for-series: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Increase delay times between aux transactions to allow for sufficient gap between multiple aux writes and aux reply. Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@amd.com> Acked-for-series: Varunkumar Allagadapa <varunkumar.allagadapa@amd.com>
Current test application for nonlive, live and mixed mode work with UCD500. Rework the application to enable different Dp1.4 monitors. Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@amd.com> Acked-for-series: Varunkumar Allagadapa <varunkumar.allagadapa@amd.com>
In Telluride by default security is enabled which causes the image selector to hang as AesSha is not initialized in the app, this change exposes the AesShaInit function so that it can be used in the image selector for initialization purposes Signed-off-by: Dasari Sharath Kumar <sharath.kumar.dasari@amd.com> Acked-by: Mounika Akula <mounika.akula@amd.com>
Add header file containing new macros for xilpm_ng library version. Also, since xilpm_ng is a new library, change the version to 1.0 in the yaml file. Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com> Acked-by: Izhar Ameer Shaikh <izhar.ameer.shaikh@amd.com>
Implemented a check to address buffer over flow issues in the TPM event function and fixed minor issues Signed-off-by: Dasari Sharath Kumar <sharath.kumar.dasari@amd.com> Acked-by: Kalyani Akula <kalyani.akula@amd.com>
In Lassen, by default eFuse clock control src is connected to MAIN_IRO_CLOCK. If we try to connect it to EMC clock, it will hang. Because it needs external clock.So removed the emc clock enable. Signed-off-by: Mounika Botcha <mounika.botcha@amd.com> Acked-for-series: Harsha <harsha.harsha@xilinx.com>
Add section attribute to DMA able buffers to point them to shared memory between PMC and PL microblaze and also fix compilation warnings Signed-off-by: Mounika Botcha <mounika.botcha@amd.com> Acked-for-series: Harsha <harsha.harsha@xilinx.com>
Output Key and PUFHD to global registers and add PUFHD decompression in example during regeneration. Signed-off-by: Mounika Botcha <mounika.botcha@amd.com> Acked-for-series: Harsha <harsha.harsha@xilinx.com>
Unnecessarly checking the IC(Iterative convergence) bit of the PUF status register before capturing the PUF ID.This caused PUF regeneration to consistently fail with a PUF_ERROR_KEY_NOT_CONVERGED error. Fixed this issue by replacing the check for the IC bit with the KR bit in the status register before proceeding to capture the PUF ID. Signed-off-by: Mounika Botcha <mounika.botcha@amd.com> Acked-for-series: Harsha <harsha.harsha@xilinx.com>
Updated changelog for 2025.1 Signed-off-by: Bhawana Sahu <bhawana.sahu@amd.com> Acked-by : Siva Addepalli<saddepal@xilinx.com>
Modify CursorBlend Api to correctly program the Cursor Coords and Cursor Size. Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@amd.com> Acked-by: Varunkumar Allagadapa <varunkumar.allagadapa@amd.com>
Txo app edited for CEA color encode. Rxo app edited for training prints.PT app edited for backward compatibility with some dp14 sources. Signed-off-by: Nishant Dhonde <nishant.dhonde@amd.com> Acked-by: Kalyanchakravathy Podalakuri<kalyanchakravathy.podalakuri@amd.com>
For versal and versalnet, checksum should not be enabled along with authentication and encryption. But for versal_2ve_2vm, due to new PDI format, checksum needs to be allowed always even when authetication and encryption are enabled. Bypassing the check for versal_2ve_2vm in PLM to allow the same. Signed-off-by: Kalyani Akula <kalyani.akula@amd.com> Acked-by: Durga Challa <durga.challa@amd.com>
…y default Update the user_compile_garbage option(fdata-sections and ffunction-sections) to be disabled by default. Signed-off-by: Sathish Kumar Kamishettigari <sathishkumar.kamishettigari@amd.com> Acked-by: Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
- For Gem0 Gem1 power request interrupt bit mask, we are using the wrong macro BITMASK. Instead, the right one is BITNMASK that can control the set bits width; while BITMASK is set bits from 0 to the bit position. Signed-off-by: Trung tran <trung.tran@amd.com> Acked-by: Izhar Ameer Shaikh <izhar.ameer.shaikh@amd.com>
The existing memory test app doesnt take care of holes in the given DDR region and generates memory test config with lowest of all base addresses as start address and highest of all high address as end address and this is resulting in memory test hang for regions with holes. Hence, add the warning message about this behavior in the memory tests app. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> Acked-by: Anirudha Sarangi <anirudha.sarangi@amd.com>
Renamed IPI access permission file as versal_2ve_2vm_access_perm.csv Signed-off-by: Preethi Kolli <preethi.kolli@amd.com> Acked-by: Durga Challa <durga.challa@amd.com>
Update EmbeddedSW License for 2025.1 Signed-off-by: Manikanta Sreeram <manikanta.sreeram@amd.com>
Include xpm_config.h to enable compiler options in decoupling flow. Signed-off-by: Madhav Bhatt <madhav.bhatt@amd.com> Acked-by: Ronak Jain <ronak.jain@amd.com>
Corrected the PCIe secondary boot mode config Signed-off-by: Sreedhar Kundella <sreedhar.kundella@amd.com> Acked-by: Mounika Akula <mounika.akula@amd.com>
Updated the order of clock primitive in the yaml file according to the config structure. Signed-off-by: S Shreesh <s.shreesh@amd.com> Acked-by: Kalyanchakravathy Podalakuri<kalyanchakravathy.podalakuri@amd.com>
…utation for R52 scenarios There is a bug in the R52 delay calculation,it does not correctly account for the frequency value fix the same. Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
…example Move the INTC interrupt vector ID under the INTC section and add GIC interrupt vector ID in the classic flow. Correct the interrupt handler name in the SDT flow to use the driver interrupt handler instead of the interrupt callback. Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com> Acked-by: Srinivas Goud <srinivas.goud@amd.com>
…tforms Memory Test application uses %lx as specifier to print 64 bit values for ARM 32 bit platforms. Instead %llx should be used. Signed-off-by: Anirudha Sarangi <anirudha.sarangi@amd.com> Acked-by: Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
…tances are not present in design This feature needs IPI in the design. Non-availability of IPI instances is causing build issue. Signed-off-by: Preethi Kolli <preethi.kolli@amd.com> Acked-by: Mounika Akula <mounika.akula@amd.com>
Signed-off-by: Bhawana Sahu <bhawana.sahu@amd.com>
Signed-off-by: Bhawana Sahu <bhawana.sahu@amd.com>
A lot of people are trying to send pull requests via github but this is not the right channel to use. Linux project is doing review over emails that's why use git@xilinx.com if you want to contribute changes to this repository. Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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This fixes both
SetRateandSetRateHz.See this https://adaptivesupport.amd.com/s/question/0D54U00008ezkpnSAA/xclkwizsetrate-sdt-on-zynq-not-working-in-vivadovitis-20241
and e5df585#commitcomment-145778417