Skip to content

projects: ad9084_ebz: Initial design #1901

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Open
bluncan wants to merge 26 commits into
base: main
Choose a base branch
from
Open

projects: ad9084_ebz: Initial design #1901

bluncan wants to merge 26 commits into from

Conversation

@bluncan
Copy link
Contributor

@bluncan bluncan commented Sep 4, 2025 •
edited
Loading

PR Description

Adds the AD9084 (Apollo) design.

Requires the following PRs to be merged to main before this one:

After they are merged, I'll rebase this branch and re-check that the projects are building.

PR Type

  • Bug fix (change that fixes an issue)
  • New feature (change that adds new functionality)
  • Breaking change (has dependencies in other repos or will cause CI to fail)
  • Documentation

PR Checklist

  • I have followed the code style guidelines
  • I have performed a self-review of changes
  • I have compiled all hdl projects and libraries affected by this PR
  • I have tested in hardware affected projects, at least on relevant boards
  • I have commented my code, at least hard-to-understand parts
  • I have signed off all commits from this PR
  • I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
  • I have not introduced new Warnings/Critical Warnings on compilation
  • I have added new hdl testbenches or updated existing ones

@bluncan bluncan mentioned this pull request Sep 4, 2025
Merged
13 tasks
FilipG24
FilipG24 reviewed Sep 8, 2025
View reviewed changes
tfcollins
tfcollins reviewed Sep 10, 2025
View reviewed changes
tfcollins
tfcollins suggested changes Sep 10, 2025
View reviewed changes
Copy link
Contributor

@tfcollins tfcollins left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Found a few invalid paths when cloned repo isn't called hdl

gastmaier
gastmaier reviewed Sep 11, 2025
View reviewed changes
@bluncan bluncan force-pushed the dev_apollo_pr branch 7 times, most recently from da69c54 to 948e151 Compare September 30, 2025 15:04
@bluncan
Copy link
Contributor Author

bluncan commented Sep 30, 2025

Updated Versal projects to use the Transceiver Subsystem which was merged to main

@bia1708
Copy link
Collaborator

bia1708 commented Oct 16, 2025

RetriggerCI

bluncan and others added 2 commits October 31, 2025 12:19
@bluncan @FilipG24
projects: ad9084_fmca_ebz: Initial commit
2d4ea46 
Adds AD9084-EBZ (Apollo) base design
for the following carriers:
 - vcu118
 - vck190
 - vpk180
 - fm87

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
@gastmaier @FilipG24
ad9084_ebz/common: Use on source
16d3222 
Allow to be sourced from testbench

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
bluncan and others added 11 commits October 31, 2025 12:19
@bluncan @FilipG24
projects: ad9084_ebz: Change spi to 3 wire
b339d85 
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
@bluncan @FilipG24
projects: ad9084_ebz: common: ad9084_ebz_bd.tcl: Migrate to inline ut…
ecfce14 
…ility cores

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
@bluncan @FilipG24
projects: ad9084_ebz: versal: Update constraints to read the lane rat…
11082f1 
…e automatically

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
@bluncan @FilipG24
projects: ad9084_ebz: Add readme file
4af6834 
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
@bluncan @FilipG24
projects: ad9084_ebz: fm87: system_project: Remove unused parameters …
1c310be 
…from description

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
@bluncan @FilipG24
projects: ad9084_ebz: versal: Update to the new Transceiver Subsystem
ffcd652 
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
@bluncan @FilipG24
library: xilinx: scripts: versal_xcvr_subsystem: Remove unused source
f802e73 
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
@bluncan @FilipG24
projects: ad9084_ebz: versal: Fix AION cs line
9b85b6b 
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
@FilipG24
projects: ad9084_ebz: vcu118: Fix AION CS line
faab8ce 
Signed-off-by: Filip Gherman <filip.gherman@analog.com>
@FilipG24
projects: ad9084_ebz: vcu118: Add support for single-link mode
75eb532 
Signed-off-by: Filip Gherman <filip.gherman@analog.com>
@FilipG24
projects: ad9084_ebz: vcu118: Improve timing for the single-link mode
d41adac 
Signed-off-by: Filip Gherman <filip.gherman@analog.com>
FilipG24 and others added 5 commits November 6, 2025 21:21
@FilipG24
projects: ad9084_ebz: vcu118: Add an extra input pipeline stage for r…
63ca9bd 
…x_jesd

Signed-off-by: Filip Gherman <filip.gherman@analog.com>
@bluncan
library: xilinx: versal_xcvr_subsystem: Add LCPLL and ILO reset logic
569134e 
The first time the board is powered on, because the reference clock
going to the transceivers is not stable until the clock chip is
programmerd, the LCPLLs are being locked wrong and the master
reset controller inside the QUADs gets stuck.

The fix is to manually reset the LCPLLs and ILOs inside the QUAD
after the clock chip is programmed.

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
@bluncan
projects: ad9084_ebz: versal: Remove unused sync_bits import
0956231 
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
@bluncan
library: xilinx: versal_xcvr_subsystem: Add option to use non consecu…
ca77d43 
…tive quads

The versal transceiver subsystem doesn't allow you to route lanes
to non-consecutive quads. This caused issues on AD9084 for use cases
where L < 4 because we couldn't connect side A to one quad and
side B to another quad.

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
@bluncan
projects: ad9084_ebz: versal: Fix side swap
4ffdb4b 
Because side B is connected to the first quad
and side A on the second one, the Versal transceiver
subsystem didn't allow us to swap them.

Becaus we now support non-consecutive quads
we can map them correctly.

We can also support building side B use cases only
for VCK190.

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
gastmaier
gastmaier reviewed Dec 9, 2025
View reviewed changes
@gastmaier
Copy link
Contributor

gastmaier commented Dec 10, 2025 •
edited
Loading

Side inversion fix working on vck190.
Configuring channel freqs now properly set the correct channel
Channel1 -> voltage0
...
Channel4 -> voltage3

@bluncan
projects: ad9084_ebz: system_project: Fix parameter typos
a70752c 
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
@bluncan
docs: ad9084_ebz: Fix project parameter name
3e6c699 
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
@bluncan bluncan requested a review from StancaPop as a code owner December 16, 2025 12:28
@bluncan
library: xilinx: scripts: versal_xcvr_subsystem: Clarity updates and …
a6dc054 
…support for non-consecutive quads

Removed duplicate code by wrapping code fragments in functions.
Non-consecutive quad mode is needed by AD9084 because its sides
are mapped backwards to the quads (side B goes to the first one,
side A goes to the second one). The Versal Transceiver Subsystem
doesn't allow you to map Quad0 to Quad1 and vice-versa so you
need to instantiate two of them with one quad each.

This method also allows us to build the VCK190 design for
side B only or to build the VCK190/VPK180 designs with
less than 4 lanes.

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
@bluncan
projects: ad9084_ebz: common: ad9084_ebz_bd: Simplify connections for…
0b19cd6 
… VCK190 Side B only

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
@bluncan
projects: ad9084_ebz: common: hsci_phy_top: Fix guideline for indenta…
e4d3ed5 
…tion

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Reviewers

@acostina acostina Awaiting requested review from acostina acostina is a code owner

@AndreiGrozav AndreiGrozav Awaiting requested review from AndreiGrozav AndreiGrozav is a code owner

@PopPaul2021 PopPaul2021 Awaiting requested review from PopPaul2021 PopPaul2021 is a code owner

@sarpadi sarpadi Awaiting requested review from sarpadi sarpadi is a code owner

@IuliaCMoldovan IuliaCMoldovan Awaiting requested review from IuliaCMoldovan IuliaCMoldovan is a code owner

@AndrDragomir AndrDragomir Awaiting requested review from AndrDragomir

@LBFFilho LBFFilho Awaiting requested review from LBFFilho LBFFilho is a code owner

@StancaPop StancaPop Awaiting requested review from StancaPop StancaPop is a code owner

@FilipG24 FilipG24 Awaiting requested review from FilipG24

@gastmaier gastmaier Awaiting requested review from gastmaier gastmaier is a code owner

1 more reviewer

@tfcollins tfcollins tfcollins requested changes

Reviewers whose approvals may not affect merge requirements

At least 1 approving review is required to merge this pull request.

Assignees

No one assigned

Labels

None yet

Projects

None yet

Milestone

No milestone

Development

Successfully merging this pull request may close these issues.

6 participants

@bluncan @bia1708 @gastmaier @tfcollins @FilipG24