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2d4ea46
projects: ad9084_fmca_ebz: Initial commit
bluncan Jan 23, 2025
16d3222
ad9084_ebz/common: Use on source
gastmaier Jun 27, 2025
462174b
fix: ad9084_ebz/common: Invalid hsci clock with ADI_PHY 1
gastmaier Jun 27, 2025
c91a283
apollo: spi: Set 4 wire spi through parameters
gastmaier Jul 1, 2025
92d7b17
ad9084_ebz/vcu118: Fix spi2 by adding a clear muxing logic between 3w…
Aug 25, 2025
b339d85
projects: ad9084_ebz: Change spi to 3 wire
bluncan Sep 12, 2025
ecfce14
projects: ad9084_ebz: common: ad9084_ebz_bd.tcl: Migrate to inline ut…
bluncan Sep 26, 2025
11082f1
projects: ad9084_ebz: versal: Update constraints to read the lane rat…
bluncan Sep 26, 2025
4af6834
projects: ad9084_ebz: Add readme file
bluncan Sep 26, 2025
1c310be
projects: ad9084_ebz: fm87: system_project: Remove unused parameters …
bluncan Sep 26, 2025
ffcd652
projects: ad9084_ebz: versal: Update to the new Transceiver Subsystem
bluncan Sep 3, 2025
f802e73
library: xilinx: scripts: versal_xcvr_subsystem: Remove unused source
bluncan Sep 30, 2025
9b85b6b
projects: ad9084_ebz: versal: Fix AION cs line
bluncan Oct 1, 2025
faab8ce
projects: ad9084_ebz: vcu118: Fix AION CS line
FilipG24 Oct 14, 2025
75eb532
projects: ad9084_ebz: vcu118: Add support for single-link mode
FilipG24 Sep 30, 2025
d41adac
projects: ad9084_ebz: vcu118: Improve timing for the single-link mode
FilipG24 Oct 31, 2025
63ca9bd
projects: ad9084_ebz: vcu118: Add an extra input pipeline stage for r…
FilipG24 Nov 6, 2025
569134e
library: xilinx: versal_xcvr_subsystem: Add LCPLL and ILO reset logic
bluncan Dec 8, 2025
0956231
projects: ad9084_ebz: versal: Remove unused sync_bits import
bluncan Dec 8, 2025
ca77d43
library: xilinx: versal_xcvr_subsystem: Add option to use non consecu…
bluncan Dec 9, 2025
4ffdb4b
projects: ad9084_ebz: versal: Fix side swap
bluncan Dec 9, 2025
a70752c
projects: ad9084_ebz: system_project: Fix parameter typos
bluncan Dec 16, 2025
3e6c699
docs: ad9084_ebz: Fix project parameter name
bluncan Dec 16, 2025
a6dc054
library: xilinx: scripts: versal_xcvr_subsystem: Clarity updates and …
bluncan Dec 16, 2025
0b19cd6
projects: ad9084_ebz: common: ad9084_ebz_bd: Simplify connections for…
bluncan Dec 16, 2025
e4d3ed5
projects: ad9084_ebz: common: hsci_phy_top: Fix guideline for indenta…
bluncan Dec 17, 2025
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2 changes: 1 addition & 1 deletion docs/projects/ad9084_ebz/index.rst
Original file line number Diff line number Diff line change
Expand Up @@ -661,7 +661,7 @@ for that project (ad9084_ebz/$carrier).
+=====================+========+========+========+========+
| JESD_MODE | 64B66B | 64B66B | 64B66B | 64B66B |
+---------------------+--------+--------+--------+--------+
| ENABLE_HSCI |:red:`-`| 1 | 1* | 1* |
| HSCI_ENABLE |:red:`-`| 1 | 1* | 1* |
+---------------------+--------+--------+--------+--------+
| REF_CLK_RATE* | 312.5 | --- | 312.5 | 312.5 |
+---------------------+--------+--------+--------+--------+
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466 changes: 350 additions & 116 deletions library/xilinx/scripts/versal_xcvr_subsystem.tcl

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7 changes: 7 additions & 0 deletions projects/ad9084_ebz/Makefile
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@@ -0,0 +1,7 @@
####################################################################################
## Copyright (c) 2018 - 2025 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################

include ../scripts/project-toplevel.mk
15 changes: 15 additions & 0 deletions projects/ad9084_ebz/README.md
Original file line number Diff line number Diff line change
@@ -0,0 +1,15 @@
# AD9084-EBZ HDL Project

- Evaluation board product page: [EVAL-AD9084](https://www.analog.com/eval-ad9084)
- HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/ad9084_ebz/index.html
- Evaluation board VADJ range: 1.2V - 3.3V

## Supported parts

| Part name | Description |
|------------------------------------------------|--------------------------------------------------------------|
| [AD9084 (Apollo MxFE)](https://www.analog.com/ad9084) | Quad, 16-Bit 28GSPS RF DAC and Quad 12-Bit, 20GSPS RF ADC |

## Building the project

Please enter the folder for the FPGA carrier you want to use and read the README.md.
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