Map tc_clk_gating to FPGA primitive for Xilinx FPGAs

[LucaRufer]

In the current version of the tech_cells_generic, the tc_clk_gating module for FPGA targets implements the clock gate as a pass-through, thus treating it as always enabled. This breaks designs that make use of functional clock gates.

In this PR, functional clock gates are mapped to the BUFGCE (Clock gate with enable) primitive. This primitive is available in all common Xilinx FPGA series:

• Ultrascale and Ultrascale+
• 7 Series and Zynq 7000
• Versal Prime
• Versal Premium
• Versal AI Core
• Versal AI Edge

In order to preserve resource usage, clock gates are only mapped to BUFGCE primitives only if they are FUNCTIONAL==1'b1. Otherwise, they are implemented as pass-through to use less of the typically limited clocking resouces.

[phsauter]

I like this and will merge it, however I would like to have the other open PRs pruned a bit before merging this because I think this may break some CIs/flows where people have a 'functional' gate that is not actually required and adding this would change the use of the clock resources enough for it to cause problems.
Essentially this could break things if there are people relying on the 'functional' part not actually being enforced.

So I will give it a more significant version bump.